A leading microelectronics firm in Switzerland is seeking a Senior Analog Mixed Signal Verification Engineer. This role involves developing verification strategies and collaborating within a multidisciplinary team to ensure high-quality product validation. Candidates should have a Master's in electrical engineering, 2-3 years of experience, and be fluent in English. Knowledge of Verilog coding and familiarity with Cadence AMS Designer is preferred. #J-18808-Ljbffr