A forward thinking Swiss fabless semiconductor company based in Lausanne are seeking to bolster their team with a talented DFT Engineer.
Responsibilities
* Lead all DFT activities for next-generation semiconductor products, owning strategy, execution, and delivery
* Define and drive DFT architectures, methodologies, and tool flows for complex multi-million-gate designs including high-speed SerDes, DDR, PCIe, and mixed-signal content
* Collaborate closely with physical design teams to define test-mode timing constraints and ensure successful convergence to tapeout
* Own test strategy and execution by working with test and production engineering teams on ATE bring-up, wafer and final test programs, silicon qualification, and HTOL readiness
* Lead silicon debug activities in the lab to resolve ATE bring-up and test issues, while mentoring and guiding DFT engineers
Requirements
* 12+ years of hands-on DFT experience covering architecture definition, implementation, ATPG, simulation, and silicon debug for complex designs
* Proven track record of delivering robust DFT solutions for large, mixed-signal and high-performance SoCs
* Strong expertise in IJTAG methodologies, hierarchical MBIST and scan insertion, scan compression, and ATPG for multiple fault models
* Deep experience defining test-mode timing constraints, analysing timing reports, and debugging timing-aware patterns using industry-standard EDA tools
* Excellent leadership, communication, scripting, and debugging skills; knowledge of SystemVerilog required, with chiplet-based design experience considered a plus
If this role is of interest please apply directly on LinkedIn or send a copy of your CV to alex@eu-recruit.com.
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