PpWe are partnering with an innovative Zürich-based tech company who are seeking a motivated Senior IC Layout Engineer, who enjoys full-custom transistor-level design and wants to help shape advanced silicon across modern process nodes. This is a full-time permanently employed position. /ppIf you love precision layout work, deep collaboration with design teams, and pushing PPA, yield, and reliability to the limit — this will be interesting. /ph3What you’ll be doing /h3pThis is a hands-on layout role with ownership from concept to tapeout. /ppYour daily work may include: /pulliCreating full-custom layouts at both transistor and block level /liliWorking on mixed-signal, custom-digital, and memory-adjacent layouts /liliPlanning floorplans and delivering DRC/LVS/PEX-clean designs on advanced nodes /liliApplying precision analog layout techniques (matching, symmetry, shielding, guarding, etc.) /liliBridging analog craft with modern FinFET/FDSOI rules and multi-patterning/EUV constraints /liliCollaborating closely with analog/custom designers, digital backend teams verification engineers /liliAutomating repetitive layout tasks using Python/Tcl (if you enjoy scripting) /liliMaintaining guidelines, documentation contributing to layout best practices /li /ulpYou will work on silicon that goes directly into cutting-edge compute architectures — impact is immediate and visible. /ph3What you’ll bring /h3pYou don’t need experience with everything below, but the more you recognize, the better: /pulli5+ years in bcustom IC layout /b covering analog, memory, or custom-digital blocks /liliExperience delivering clean layouts on badvanced nodes (sub-28nm, FinFET/FDSOI) /b /liliStrong understanding of analog layout fundamentals: /liliCurrent-mirror symmetry /liliMatching shielding /liliGuard rings substrate isolation /liliAbility to work confidently with design backend teams on extraction, timing, IR EM topics /liliFamiliarity with modern layout verification flows (DRC, LVS, PEX) /liliGood communication, structured documentation habits a collaborative mindset /li /ulh3Bonus experience (nice to have but not required) /h3ulliExperience with SRAM periphery, redundancy or memory-adjacent layouts /liliKnowledge of scan/MBIST routing or macro-level integration /liliExposure to DFM/DFY, ESD/latch-up, or EM/IR reliability checks /liliScripting experience in Tcl or Python for automation /li /ul /p #J-18808-Ljbffr