Job Title: IC Layout R&D Engineer My client is seeking an IC Layout R&D Engineer to support IC layout and CAD automation for cutting-edge semiconductor projects.
Responsibilities include:
Manage and support EDA back-end analog tools (Cadence, Siemens) and design flows.
Execute IC layout tasks for integration and tape-out.
Develop automation solutions to enhance design efficiency.
Validate process design kits (PDKs) and maintain CAD libraries.
Support IC layout outsourcing and ensure adherence to design standards.
Ideal candidate will have experience in:
Hands-on experience in IC layout, including LVS, DRC, and ERC verification.
Knowledge of advanced CMOS processes.
Proficiency in Linux, scripting languages (Python, bash, Skill), and version control tools (e.g., SVN).
Strong problem-solving skills and a collaborative mindset.
This position is open to applicants with the right to work in Switzerland, including EU and UK nationals.
If you are an experienced IC Layout Engineer with CAD experience, please contact Parm Shergill for more information.
Additional Details: Seniority level: Mid-Senior level
Employment type: Full-time
Industry: Semiconductor Manufacturing and Engineering Services
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