An experienced Digital Verification Lead Engineer is required to lead verification strategy and deliver high:quality digital designs in collaboration with global engineering teams.
Locations: Switzerland (Lausanne) UK (Reading / Northampton) Germany (Dortmund) Denmark
Department: Engineering
Work Model: Hybrid
Overview
We are seeking an experienced Digital Verification Lead Engineer to own and lead verification activities for complex digital designs. This role combines hands:on technical expertise with leadership, working closely with design and validation teams across multiple sites.
Key Responsibilities
:Act as verification lead on assigned projects
:Provide technical leadership and mentoring to verification engineers
:Define, maintain, and execute verification plans based on design specifications
:Plan, schedule, and track verification activities and team tasks
:Develop and implement verification methodologies and standard debug flows
:Participate in design and verification reviews
:Maintain verification environments; track, debug, and close issues
:Collaborate closely with design teams on verification and validation
:Apply modern tools, techniques, and technologies in verificationSkills and Expertise
:Strong communication skills and collaborative working style
:Proficient scripting skills with experience in regression setup and management
:Deep understanding of simulation and verification environments and debugging techniques
:Experience with Gate:Level Simulation (GLS) and debug
:Strong knowledge of metrics:driven verification and coverage closure
:Testbench development using modern methodologies (e.g. UVM)
:Experience with 3rd:party VIP, emulation, FPGA prototyping, or Assertion:Based Verification (advantageous)Experience Required
:7+ years' experience in digital verification within the semiconductor industry
:Experience leading and coordinating verification teams across multiple locations
:Proven track record verifying complex, high:volume designs
:Strong judgement balancing quality, risk, and delivery schedules
:Experience with constrained:random verification
:Familiarity with SerDes and high:speed protocols (e.g. PCIe, USB, DisplayPort) is a plus
:Experience managing and coordinating external sub:contractorsEducation
:Bachelor's degree in Electronics or Electrical Engineering (or equivalent or higher)