Job description
Responsibilities
1. Developing the mixed signal verification strategy and its related test bench maintaining Ultra Low Power, applicable on top circuit and IP level
2. Build and re-use the necessary Verilog-A models behavioral models, monitors and checkers for full system verification suites
3. Work with system architect to develop system tests, stimulating ASICs from IC boundary, to ensure functionality with all types of data in all modes of operation
4. Develop automatic regression of verification suites using Cadence AMS Designer verification flow in Xcelium
5. Manage bug tracking and coverage
6. Constantly improve the verification methods and strategy to cut down product time to market while maintaining strong validation quality