A leading semiconductor company is seeking a Lead DFT Engineer in Lausanne, Switzerland to lead design-for-test strategies for complex ICs. The ideal candidate will have over 12 years of experience in DFT architecture and implementation, proven delivery in high-volume silicon, and strong skills in SystemVerilog, IJTAG, and ATPG. This role offers a hybrid work environment with opportunities for technical leadership and mentorship. #J-18808-Ljbffr