We are a growing semiconductor engineering organisation developing complex, high-performance silicon used in next-generation electronic systems. We’re looking for a Lead DFT Engineer to own design-for-test strategy and execution for upcoming products, working in a hybrid setup in Switzerland.
What You’ll Do
* Lead DFT architecture, methodology, and tool flows for large, complex ICs
* Drive DFT solutions for designs combining digital, analog, and high-speed interfaces
* Define and close test mode timing constraints in collaboration with physical design
* Own test strategy and planning across wafer and final test
* Guide ATPG and functional/structural pattern development
* Support ATE bring-up, silicon debug, and production ramp
* Mentor engineers and provide hands-on technical leadership
What We’re Looking For
* 12+ years of experience in DFT architecture, implementation, and verification
* Proven delivery of DFT for complex, high-volume silicon
* Strong experience with:
* IJTAG, hierarchical scan, MBIST, and scan compression
* ATPG, fault coverage analysis, and timing-aware pattern debug
* Test mode constraint definition and analysis
* Experience with DFT, timing, and simulation EDA tools
* Solid SystemVerilog and scripting skills
* Experience leading and mentoring engineers
* Exposure to chiplet-based designs is a plus
Education
* Degree in Electrical Engineering, Electronics, Computer Engineering, or similar
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