Description
The Role
We are looking to expand our team with a Senior Digital IC Verification Engineer. You will help us develop IP for next generation Automotive, Industrial & Medical products. The successful candidate will participate in the design of complex mix-signal IPs and have familiarity with analog blocks such as DACs, ADCs, PLL and wireless interface etc.
Responsibilities
What You'll Do
* Define the verification strategy and the detailed verification plans for blocks and systems
* Coordinate/lead the verification activities in the project teams
* Develop SystemVerilog/UVM environments for blocks and top-level SoCs
* Debug functional errors in RTL
* Participate to verification methodology improvement activities
Qualifications
What You'll Need
* Minimum BS/MS in Electrical Engineering or related technical field
* Minimum 3 years of digital verification experience
* Solid understanding of verification best practices such as verification planning, requirements tracking, and functional coverage
* In-depth knowledge and some years of proven experience in state-of-the-art verification methodologies (e.g. UVM), constrained random driven verification, assertion based verification, test environment architecture & creation, regression management, coverage collection
* Excellent English written and verbal communication skills
* Eligibility to work in Switzerland
What Else You May Bring
* Experience with:
* Project/task leadership
* Verification of signal processing components
* 3rd party verification IP deployment
* Programming skills – Python, Tcl, embedded software
* Knowledge of French