Advanced R&D Analog Design Engineer
CDI à 100% de suite ou à convenir. Application online only – mention source ORP.
At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO‑over‑copper technology powers a high‑performance, chiplet‑based AI memory fabric that is both scalable and energy‑efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra‑low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
Job Title
Analog Design Engineer (Advanced Research and Development Department)
Key Responsibilities
Develop block‑level specifications and models for target designs
Design, model, and verify custom analog circuits in advanced technology nodes
Lead layout design and development, including floor‑planning, guiding layout engineers, and post‑layout verification
Perform design verification at different levels (pre‑ and post‑layout, variation‑aware)
Collaborate with design and layout engineers, architects, chip‑level integration engineers, and system‑level designers
Support post‑silicon lab bring‑up, debug, characterization, and productization
Produce progress reports, analysis reports, design, modeling, and verification reports
Participate in developing concept‑level architectures and circuits
Skills
Deep understanding of design and layout techniques for high‑speed and high‑precision circuits
Strong problem‑solving and analytical skills
Experience developing testbenches and simulation setups to analyze performance of target circuits and systems
Proficiency in layout techniques such as matching, parasitic estimation and reduction, and deep‑submicron related issues
Advanced user of EDA tools for design and verification (preferably Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitic extraction, EM and IR drop tools, and ESD analysis)
Self‑motivated with a strong sense of ownership and responsibility
Ability to manage workload, schedules, and report to internal management and technical teams
Excellent communication and reporting skills
Experience
5+ years of experience in design and layout of analog and mixed‑signal circuits, especially high‑speed and high‑precision circuits (e.g., multi‑gigabit serial data‑link transceivers, RF circuits, equalizers, clock generators, PLLs, clock and data recovery circuits, data converters (ADC or DAC), biasing and bandgap circuits)
MSc or PhD in electronics/electrical engineering (or equivalent)
Experience with modern semiconductor process technologies (e.g., CMOS 28 nm, FinFET 16/14 nm, 7 nm)
Experience in high‑level modelling, top‑level simulations, and signal integrity
Solid background in signal processing and communications
Location & Employment
Work location : 1025 St‑Sulpice VD (VD)
Additional information on the place of work : Innovation Park, EPFL
Workload : 100%
Employment start : Immediately
Employment duration : Permanent
Qualification : Skilled
Work experience : More than 3 years
Education : Bachelor's degree from a university or equivalent
French : Orally – Good knowledge; Written – Good knowledge
English : Orally – Very good knowledge; Written – Very good knowledge
Application method : Online form
If this is the role you have been looking for and you want to be part of a growing company with an exciting future, we would really love to hear from you. Together we Kandou it!
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