Job description
Responsibilities
* Developing the mixed signal verification strategy and its related test bench maintaining Ultra Low Power, applicable on top circuit and IP level
* Build and re-use the necessary Verilog-A models behavioral models, monitors and checkers for full system verification suites
* Work with system architect to develop system tests, stimulating ASICs from IC boundary, to ensure functionality with all types of data in all modes of operation
* Develop automatic regression of verification suites using Cadence AMS Designer verification flow in Xcelium
* Manage bug tracking and coverage
* Constantly improve the verification methods and strategy to cut down product time to market while maintaining strong validation quality
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