A semiconductor company in Zurich is seeking a Senior Physical Design Engineer to lead complex IP and SoC designs. The role involves driving Static Timing Analysis, timing ECOs, and power-grid planning. Candidates must have strong expertise in timing closure or power/IR-drop sign-off, proven experience with successful tapeouts, and scripting skills in Tcl or Python for flow automation. This position offers the opportunity to work on advanced process nodes while delivering robust silicon. #J-18808-Ljbffr