Digital Design Engineer, CH, UK DE, DK
CDI to 100% immediately or to be agreed.
Postulation uniquement en ligne - merci de mentionner sous source (ORP)
hallenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip‑chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale‑up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.
We are actively seeking a resourceful Digital Design Engineer, based in either UK (Reading/Northampton), Germany, Denmark or Lausanne, Switzerland.
Key Responsibilities
Define block‑and top‑level specifications for high‑speed digital circuits that meet key performance targets based on system‑level requirements. Review and challenge architectural specifications to ensure robustness and efficiency. Specify analog/digital interfaces in close collaboration with analog and mixed‑signal design teams. Design, implement, and test RTL code. Collaborate closely with verification and physical implementation engineers to ensure functionality, timing, area, and power goals are met. Support post‑silicon activities, including lab bring‑up, debugging, characterization, and productization. Manage workload and schedules, providing regular updates to internal management and external customers.
Skills
Strong analytical ability to translate system‑level requirements into design specifications. Hands‑on design experience in PHY design for high‑speed interfaces (e.g., USB4, PCIe) is preferred. Proficient RTL coding skills (SystemVerilog preferred). Advanced knowledge of high‑speed and low‑power design techniques. Familiarity with signal processing techniques is a plus. Proficiency in scripting and tool automation (Python, tcl, …). Solid understanding of clock domain crossing (CDC) issues and mitigation techniques. Experience analysing synthesis and static timing analysis (STA) results. Knowledge of verification methodologies, particularly UVM, is an advantage. Self‑motivated, with a strong sense of ownership and accountability. Excellent communication and teamwork skills.
Experience
MSc in Electrical or Electronics Engineering (or equivalent/higher degree). 5+ years of experience in the semiconductor industry. Strong technical background in the design of high‑speed digital circuits using advanced CMOS technologies. Exposure to analog design techniques is a plus. Familiarity with Cadence design tools is an advantage.
If this is the role you have been looking for and want to be part of a growing company with an exciting future, we would really love to hear from you. Together We Kandou It!
Work location 1025 St‑Sulpice VD (VD)
Workload 100%
Employment start Immediately
Employment duration Permanent
Qualification skilled
Work experience More than 3 years
Education Master’s degree from a university of applied sciences or equivalent
English Orally: Very good knowledge; Written: Very good knowledge
By online Online form
#J-18808-Ljbffr