ASIC Digital Designer (EP-ESE-ME-2025-85-LD)
At CERN, the European Organization for Nuclear Research, physicists and engineers are probing the fundamental structure of the universe. Using the world's largest and most complex scientific instruments, they study the basic constituents of matter—fundamental particles that are made to collide together at close to the speed of light. The process gives physicists clues about how particles interact and provides insights into the fundamental laws of nature. Find out more on http://home.cern.
Introduction
We are seeking a talented and experienced ASIC Digital Designer with expertise in digital-on-top (DoT) implementation and System-on-Chip (SoC) design techniques. The candidate will contribute to the development of ASICs for particle physics experiments, working with advanced planar CMOS technologies (e.g., 65nm, 28nm) in collaboration with system architects, analogue and mixed-signal design teams, and verification engineers.
You will join the Electronic Systems for Experiments Group (ESE) of the Experimental Physics Department (EP), which designs electronic systems, including ASICs, for CERN experiments and provides related electronics services. The Microelectronics section (ME) develops analogue and digital application-specific integrated circuits for CERN's particle detector systems.
Functions
As an ASIC Digital Designer, you will:
1. Perform full-chip digital integration and verification:
o incorporate custom logic, third-party IP blocks, and standard interfaces
o manage clock/reset domains
o apply low power design techniques
2. Develop RTL code ensuring synthesizable and reusable designs.
3. Develop high-level architectures for ASIC designs, including SoC partitioning, data paths, control logic, and interfaces.
4. Write testbenches and run simulations to verify design functionality.
Qualifications:
* Master's degree, PhD, or equivalent experience in Electronics Engineering or a related field.
Experience:
* Demonstrated experience in hierarchical Digital-On-Top ASIC integration and implementation (from RTL to GDS), including functional and physical verification.
* Proven experience with advanced EDA tools and deep submicron CMOS technologies, including Cadence tools and process nodes such as 65nm, 28nm, or smaller.
* Experience in RTL design (Verilog/SystemVerilog) and scripting languages (Python, TCL, Shell).
* Experience in Logic Synthesis, Timing Closure, Static Timing Analysis, and Power Integrity Analysis.
* Experience in physical design floor planning, cell placement, routing, and sign-off checks (DRC, LVS).
* Experience in developing test benches for behavioural and functional simulations.
* Knowledge in integrating Analog and Digital IPs, managing interconnects, planning clock/reset domains, and assigning timing constraints.
* Knowledge in integrating design-for-testability (DFT) structures and employing design-for-manufacturing (DFM) methodologies.
Additional valued fields include:
* Understanding of SoC design techniques, bus protocols (AXI, AHB, APB).
* Knowledge of RISC-V ISA and core integration.
* Experience with Microarchitecture design: FSMs, pipelining, ALUs, memory controllers.
* Experience with debugging and linting tools (Verilator, etc.).
* Experience with FPGA prototyping for SoC validation.
* Knowledge of design methodologies for radiation effects mitigation (SEE and TID).
* Design and simulation of digital microelectronic circuits.
* Knowledge of high-level description languages and tools.
* Knowledge of signal integrity techniques.
* Experience in testing and measuring digital circuits.
Soft skills include teamwork, results-oriented planning, adaptability, effective communication, and knowledge sharing.
Fluency in spoken and written English, with a commitment to learn French.
Eligibility and Closing Date:
CERN values diversity and welcomes applications from all Member States and Associate Member States. The position will be filled as soon as possible; applications should be submitted by 25.05.2025, 23:59 CEST.
Employment Conditions:
* Limited duration contract (5 years), with potential for indefinite employment.
* Working hours: 40 hours/week.
* Work may involve radiation areas, nights, Sundays, and holidays.
* Job grade: 6-7.
* Reference: EP-ESE-ME-2025-85-LD.
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