**All applicants must have the right to work in Switzerland**
Our client, a cutting-edge semiconductor company working on next-generation compute architectures, is looking for a Senior Physical Design Engineer to take ownership across complex IP and SoC designs. This is a key technical role focused on high-quality implementation, collaboration, and delivering robust silicon on advanced process nodes.
As a Senior Physical Design Engineer, you’ll be responsible for driving Static Timing Analysis, timing ECOs, power-grid planning, IR-drop analysis, and correlation across synthesis, place-and-route, and sign-off.
Required experience:
* Strong expertise in either timing closure or power/IR-drop sign-off.
* Proven experience in 2+ successful tapeouts
* Solid understanding of STA, multi-clock designs, and hierarchical timing closure.
* Proven hands-on experience with synthesis and P&R flows on advanced nodes.
* Experience in power-grid design, IR-drop analysis
* Proficiency in scripting (Tcl, Python) for flow automation and report generation.
Tel - 01189073075
LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/
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