A leading semiconductor company based in Lausanne, Switzerland is seeking a digital design engineer.
Key Responsibilities
* Lead verification activities across assigned projects, providing direction and ensuring alignment with design goals.
* Offer technical leadership and mentorship to team members to strengthen overall verification capability.
* Create comprehensive verification plans derived from detailed design specifications.
* Manage project timelines by planning work, allocating tasks, and monitoring progress across the team.
* Develop and maintain robust verification methodologies, environments, and standard debug flows while collaborating closely with design teams.
Requirements
* Strong communication skills and the ability to work effectively in a multi-site, team-oriented environment.
* Proficiency in scripting, regression setup, and management, with a solid understanding of simulation, debugging, and verification flows (including gate-level simulation).
* Expertise in metrics-driven verification, testbench development (UVM or similar), and use of third-party VIP; exposure to emulation or FPGA prototyping is a plus.
* Minimum of 7 years’ experience in semiconductor design verification, with a proven record validating complex, high-volume designs and balancing schedule vs. quality trade-offs.
* Experience leading teams and coordinating external resources, with familiarity in constrained-random testing, SerDes, and protocols such as PCIe, USB, or DisplayPort.
If this role is of interest please apply directly on LinkedIn or send a copy of your CV to alex@eu-recruit.com.
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Seniority level
* Mid-Senior level
Employment type
* Full-time
Job function
* Information Technology
Industries
* Software Development
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