A leading semiconductor company in Switzerland is seeking a Technical Lead for Physical Design (RTL to GDSII). The candidate will own the end-to-end implementation for complex IP/SoC subsystems and lead a backend engineering team to define methodologies and quality metrics. Responsibilities include managing synthesis, floor planning, integration of custom macros, and engaging with foundries on PDK updates. This role demands over 10 years in ASIC physical design and deep expertise in related tools, ensuring a strong candidate pool for this high-impact position.
#J-18808-Ljbffr