A leading semiconductor design firm in Zürich is seeking an experienced Layout Engineer to own transistor-level and block-level layouts for advanced IP. The ideal candidate will have over 5 years of experience in custom layouts and a solid grasp of analog techniques. Responsibilities include interfacing with design teams and automating design processes, ensuring high-quality outcomes on sub-28 nm nodes. This role offers the opportunity to make a significant impact in a collaborative environment. #J-18808-Ljbffr