You will work closely with hardware and with early customers, turning a silicon capability into a developer-friendly product. One of your primary responsibilities will be to understand how our hardware works and provide feedback to the hardware designers on how to simplify its use and improve its performance from a system perspective. You will drive the growth of the team, set the bar for quality and documentation, and ship on a predictable cadence.
What you’ll do
Own the software development from a management perspective, being responsible for the deliverables and their quality, distributing the workload among team members, prioritizing the various activities, and reviewing the teamwork.
Be responsible for ensuring the correct exchange of information between the hardware and software teams, and handle the software part of our hardware/software co-design. Work with the architecture and custom design teams on data flows, programming models, and supported functionalities.
Deliver a clean programming model, drivers, kernels, and examples; package them for real-world projects, and maintain stability as hardware evolves.
Define the compiler development, establish priorities, and plan functionalities based on customer requirements.
Create integration kits, reference designs for MCUs and accelerators, ready‑to‑build projects, and step‑by‑step guides that our customers and partners can follow.
Grow the team: hire, mentor, design, and code reviews, and set clear ownership boundaries.
Outcomes (first 18 months)
A production‑level software suite with code, docs, and references for one MCU platform and one accelerator.
A compiler prototype that maps foundational AI algorithms and related layers to ComputeRAM with clear speed‑up and memory savings, documented end‑to‑end.
A benchmark and profiling suite, with visible improvements in latency and energy across releases
Requirements
7+ years building low‑level software or compilers; strong C++ and Python
A track record of shipping complete projects end‑to‑end,
Experience with roadmaps and reviews. Ability to work and lead independently, starting from top‑level goals as input and producing a complete development plan, including planning (Jira, MS Project)
Hands‑on with at least one of: MLIR/LLVM passes, code generation, graph compilers, or high‑performance DSP libraries.
Ability to deal with hardware‑specific language, read specs, define clean APIs, and negotiate trade‑offs.
Nice to have
Experience integrating with TensorFlow Lite for Micro.
Experience with packaging software for external developers.
MCU bring‑up expertise and familiarity with toolchains
Deep learning and AI understanding and expertise, including quantization and edge‑specific optimizations
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