Job description
Responsibilities
* Developing the mixed signal verification strategy and its related test bench maintaining Ultra Low Power, applicable on top circuit and IP level
* Build and re-use the necessary Verilog-A models behavioral models, monitors and checkers for full system verification suites
* Work with system architect to develop system tests, stimulating ASICs from IC boundary, to ensure functionality with all types of data in all modes of operation
* Develop automatic regression of verification suites using Cadence AMS Designer verification flow in Xcelium
* Manage bug tracking and coverage
* Constantly improve the verification methods and strategy to cut down product time to market while maintaining strong validation quality
Profile
* Strong autonomy in his field and capability for team work.
* Ability to contribute to a multi-disciplinary team in a constructive way.
* Masters in electrical / electronic engineering.
* At least 2-3 years' experience in similar position and industry and eager to progress.
* Used to work in multicultural team environment.
Professional requirements
* A strong candidate has several years of design experience in analog and/or mixed signal and is eager to participate to all steps of product development, from definition to ramp up
* Front-end digital design experience (system, architecture, verification) in mixed signal environment
* Knowledge of Verilog/SV/VHDL verification coding is a plus
Languages
* Fluent in English, oral & written.
* Knowledge of French and/or German would be an asset.