A leading semiconductor company based in Lausanne, Switzerland are seeking to bolster their team with a talented Analog Layout Engineer.
Responsibilities
* Design and verify analog circuits, cells, blocks, and IP for multi-Gigabit high-speed chip-to-chip communication links (SerDes ≥28Gb/s and/or memory IO) in advanced semiconductor nodes.
* Layout and validate very high-speed analog circuits, ensuring performance and reliability.
* Collaborate closely with the design team to understand specifications and implement optimized solutions.
* Support IP and chip-level integration, including interactions with customers regarding requirements and delivery.
* Gain experience with flip-chip packaging technologies and contribute to related design considerations.
Requirements / Experience
* Proven experience in custom analog layout for multi-Gigabit serial data-link transceivers or HF/RF circuits.
* Expertise in high-speed circuit layout, including amplifiers, oscillators, PLLs/DLLs, biasing networks, buffers, regulators, filters, and data converters.
* Strong understanding of high-speed layout techniques: matching, parasitic minimisation, power grids, ESD, and other semiconductor constraints.
* Familiarity with advanced process technologies (28nm, 14/16nm, 7nm) and EDA tools like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitic extraction, EM/IR drop, and ESD checks.
* Self-motivated team player with semiconductor physics background, capable of managing workload, schedules, and communicating effectively with internal and external stakeholders.
If this role is of interest please apply directly on LinkedIn or send a copy of your CV to alex@eu-recruit.com.
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Seniority level
* Associate
Employment type
* Full-time
Job function
* Information Technology
Industries
* Software Development and IT System Custom Software Development
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