Overview
A fantastic opportunity for an EDA/CAD Engineer to join an innovative leader in high-speed and energy-efficient chip-chip link solutions, critical to the evolution of the electronics industry.
Choice of Location in Reading (UK) or Lausanne (Switzerland).
Responsibilities
* Manage and maintain an integrated analog/digital EDA environment, including installation, configuration, and support of tools such as Cadence Virtuoso, Synopsys platforms, and Siemens Calibre/AFS.
* Flow development & automation: design, automate, and validate robust CAD flows for simulation, physical verification, parasitic extraction, and reliability analysis.
* Methodology support: provide expert guidance to analog and digital design engineers; troubleshoot tool issues; optimize design methodologies for performance and quality.
* PDK installation & support: contribute to installation, qualification, and deployment of PDKs for advanced technology nodes.
* Design enablement: create and maintain clear documentation, training materials, and scripts so teams can use tools and flows effectively.
* Continuous improvement: proactively identify bottlenecks and implement solutions that improve productivity, accuracy, and turnaround time.
About you
* Strong programming skills: Shell, Python, Perl, Tcl, SKILL; ability to develop simple GUIs; Make-based build automation.
* Solid understanding of the full chip-design lifecycle and digital, analog, and mixed‑signal IC design flows.
* Excellent problem‑solving skills with the ability to prioritize and manage multiple tasks in a fast‑paced environment.
* Proficient in EDA/CAD flow development while balancing stakeholder needs (quality, schedule, and compute efficiency).
Experience
* Bachelor or Master of Science Degree in Electrical Engineering, Computer Engineering, or Computer Science.
* 10+ years in an EDA/CAD engineering role supporting both analog and digital IC design teams.
* Proven experience at advanced technology nodes and associated PDKs; practical knowledge of industry-standard methodologies, tool licensing, revision control, and release management.
* Hands-on expertise with key tools across: Analog/RF (Cadence Virtuoso Schematic/Layout, ADE, Spectre/APS/AFS), Physical Verification (Siemens Calibre; Cadence Pegasus), Parasitic Extraction (Cadence Quantus), and Digital Implementation (Synopsys Design Compiler & IC Compiler II; Cadence Innovus).
* Deep data management experience (Git, Cliosoft) enabling consistent, flexible multi-project/multi-discipline flow setup and database tagging.
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Seniority level
Mid-Senior level
Employment type
Full-time
Job function
Design and Engineering
Industries
Semiconductor Manufacturing, Appliances, Electrical, and Electronics Manufacturing, and Computers and Electronics Manufacturing
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