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Soc / asic design engineer (ep-ese-me-2025-132-grap)

Genf
CERN
Design
Inserat online seit: 13 September
Beschreibung

Job DescriptionYour responsibilitiesEmerging state-of-the-art microelectronic technologies and electronics design methodologies are promising to revolutionize the way we design and implement readout and control circuits for on-detector electronics in particle physics experiments.CERN and its EP-ESE/ME section are actively exploring the feasibility of utilizing RISC-V processing cores and System-on-Chip (SoC) design methodologies for future on-detector electronics.Responsibilities:Create System-on-Chip topologies using the open-source SOCMake tool, currently being developed at CERN.Emulate the operation of the designed SoC topologies and assess their performance on FPGA development platforms as well as on silicon prototypes.Design IP blocks, integrate them into the SOCMake tool, and validate their functionality through simulation and emulation techniques.Incorporate fault-tolerant design strategies into the SoC and IP block development.Your profileSkills:Strong understanding of digital logic design.Experience with Finite State Machines (FSMs).Experience in Verilog and/or VHDL for RTL design.Knowledge of SystemVerilog for modeling and verification.Experience with FPGA prototyping.Knowledge of Radiation Effects on silicon and hardening by design techniques.Experience working with RISC-V or ARM architectures and writing firmware in C/C++ for SoC integration.Proficiency in Python programming and Shell scripting in Linux environments.Spoken and written English, with a commitment to learn French.Eligibility criteria:You are a national of a CERN Member or Associate Member State.You have a professional background in Electronics Engineer (or a related field) and have either:a Master's degree with 2 to 6 years of post-graduation professional experience;or a PhD with no more than 3 years of post-graduation professional experience.You have never had a CERN fellow or graduate contract before.Additional InformationJob closing date: 21.09.2025 at 23:59 CEST.Contract duration: 12 months, with a possible extension up to 36 months maximum.Working hours: 40 hours per weekTarget start date: 01-November-2025Job reference: EP-ESE-ME-2025-132-GRAPField of work: Electrical or Electronics EngineeringWhat we offerA monthly stipend ranging between 6287 and 6911 Swiss Francs per month (net of tax).Coverage by CERN's comprehensive health scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund.Depending on your individual circumstances: installation grant; family, child and infant allowances; payment of travel expenses at the beginning and end of contract.30 days of paid leave per year.On-the-job and formal training at CERN as well as in-house language courses for English and/or French.About usAt CERN, the European Organization for Nuclear Research, physicists and engineers are probing the fundamental structure of the universe. Using the world's largest and most complex scientific instruments, they study the basic constituents of matter - fundamental particles that are made to collide together at close to the speed of light. The process gives physicists clues about how particles interact, and provides insights into the fundamental laws of nature. Find out more on http://home.cern.We are on a Quest. A Journey into discovery like no other. Bring your expertise to our unique work and develop your knowledge and skills at pace. Join world-class subject matter experts on unique projects, in a Quest for greater knowledge and deeper understanding.Begin your CERN Quest. Take Part!Diversity has been an integral part of CERN's mission since its foundation and is an established value of the Organization. Employing a diverse workforce is central to our success.
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Home > Stellenanzeigen > Kunst und Kultur Jobs > Design Jobs > Design Jobs in Genf > SoC / ASIC Design Engineer (EP-ESE-ME-2025-132-GRAP)

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