Senior Analog IC Layout Engineer with finFET experience Salary: Very Attractive Rate
Location: N/A
Contract
Qualifications: Minimum 7 years' experience in Analog IC Layout
Experience working on high-speed layouts
Experience working on speeds up to or exceeding 25 Gb/sec
Experience with finFET technology, specifically TSMC down to 16nm
Proficiency with Cadence tools
Additional Requirements: Experience as a Senior Analog Layout Engineer or similar role
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Senior Analog & AMS Recruitment Specialist
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