Working for a cutting-edge semiconductor company, I have a brand-new Senior Digital Design Verification opportunity to work on the latest high-speed communication ASIC technologies.
You will be part of key R&D projects for complex IP - working closely with designers, architects, and other verification engineers in the wider business.
Salary: 110-120k CHF
Must have skills: University degree - BSc / MSc / PhD in Electronics, Microelectronics, Physics or Computer Science
Industry experience in digital verification - for FPGA / ASIC (VHDL and / or Verilog, SystemVerilog)
Good language & communication skills in English
Strong coding skills - Python / C / C++ / SystemC
UVM environments, libraries, and complex test-benches for digital IPs
Bonus / "nice-to-have" skills: Definition of complex digital architecture
High-speed digital connectivity and protocols - SerDes, Ethernet, USB, PCIe, AMBA / AXI, MAC, PHY, cache coherency - MESI
Testing / validation
Matlab / Simulink modelling experience
Confident software coding skills - C++ / Python etc
Formal / software verification - Jasper Gold, OneSpin, SVA - SystemVerilog assertions
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