PpJob Openings Senior IC Layout Engineer Custom Analog / Mixed-Signal /p h3About the job Senior IC Layout Engineer Custom Analog / Mixed-Signal /h3 pWe are partnering with an innovative Zürich-based tech company who are seeking a motivated Senior IC Layout Engineer, who enjoys full-custom transistor-level design and wants to help shape advanced silicon across modern process nodes. This is a full-time permanently employed position. /p pIf you love precision layout work, deep collaboration with design teams, and pushing PPA, yield, and reliability to the limit this will be interesting. /p pbWhat you will be doing /b /p pThis is a hands-on layout role with ownership from concept to tapeout.br/Your daily work may include: /p ul li️ Creating full-custom layouts at both transistor and block level /li liWorking on mixed-signal, custom-digital, and memory-adjacent layouts /li li️ Planning floorplans and delivering DRC/LVS/PEX-clean designs on advanced nodes /li liApplying precision analog layout techniques (matching, symmetry, shielding, guarding, etc.) /li liBridging analog craft with modern FinFET/FDSOI rules and multi-patterning/EUV constraints /li liCollaborating closely with analog/custom designers, digital backend teams verification engineers /li liAutomating repetitive layout tasks using Python/Tcl (if you enjoy scripting) /li liMaintaining guidelines, documentation contributing to layout best practices /li /ul pYou will work on silicon that goes directly into cutting-edge compute architectures impact is immediate and visible. /p pbWhat you will bring /b /p pYou do notneed experience with everything below, but the more you recognise, the better: /p ul li5+ years in bcustom IC layout /b covering analog, memory, or custom-digital blocks /li liExperience delivering clean layouts on badvanced nodes (sub-28nm, FinFET/FDSOI) /b /li liStrong understanding of analog layout fundamentals: /li liCurrent-mirror symmetry /li liMatching shielding /li liGuard rings substrate isolation /li liAbility to work confidently with design backend teams on extraction, timing, IR EM topics /li liFamiliarity with modern layout verification flows (DRC, LVS, PEX) /li liGood communication, structured documentation habits a collaborative mindset /li /ul pb⭐ /bbBonus experience (nice to have but not required) /b /p ul liExperience with SRAM periphery, redundancy or memory-adjacent layouts /li liKnowledge of scan/MBIST routing or macro-level integration /li liExposure to DFM/DFY, ESD/latch-up, or EM/IR reliability checks /li liScripting experience in Tcl or Python for automation /li /ul pbLocation setup /b /p pZurich, Switzerlandbr/Hybrid work model (mix of onsite collaboration and home office) /p /p #J-18808-Ljbffr