Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.
We are actively seeking a resourceful Digital Verification Lead Engineer, based in either Lausanne, Switzerland, UK (Reading/Northampton), Germany (Dortmund), or Denmark.
Key Responsibilities Act as verification lead on projects
Provide technical leadership & mentoring
Prepare design verification plan based on design specifications
Plan and schedule projects, assign and track tasks for team members
Develop design verification methodologies and implement standard debug flows
Participate in design reviews
Maintain design verification environment and track & close design bugs
Work with designers in verification and validation of circuit designs
Utilize the latest techniques, tools, and technologies for design verification activities
Skills Excellent communication skills, strong team player
Good scripting techniques, experience with regression setup & management
Deep understanding of simulation and verification environments, including debugging techniques.
Experience with Gate Level Simulation flows and debug.
Strong knowledge on Metrics-driven verification (incl. verification planning and coverage closure)
Experienced with test bench development using the latest methodologies
Experience with 3rd party VIP usage and test development (a plus)
Experience with emulation platforms and/or FPGA prototyping (a plus)
Experience with Assertion Based Verification (a plus)
Experience 7+ years’ experience in the semiconductor industry
Experience in leading and managing a team across multiple sites
Proven track record in verifying complex designs (preferably in high volume applications)
Skilled in trade-offs between quality and schedule
Experience in constrained random test bench development
Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous
Extensive digital verification background with some UVM experience
Coordinate and oversee external sub-contractors to scale up verification workloads
Education Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)
If this is the role you have been looking for and you want to be part of a growing Company, with an exciting future then we would really love to hear from you. Together We Kandou It !
Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/
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