A leading semiconductor company in Lausanne, Switzerland, is seeking a resourceful DFT Engineer. The candidate will focus on hierarchical MBIST and scan insertion, ATPG pattern generation, and debugging silicon issues. Applicants should have over 5 years of DFT experience, including IJTAG methodologies and debugging skills. You will work alongside test and production teams to ensure high coverage metrics and contribute to innovative chip solutions. #J-18808-Ljbffr