ASIC Digital Designer (EP-ESE-ME-2025-85-LD)
* Contract
At CERN, the European Organization for Nuclear Research, physicists and engineers explore the fundamental structure of the universe using the world's largest and most complex scientific instruments. They study the basic constituents of matter—fundamental particles—by colliding them at close to the speed of light. This process provides clues about particle interactions and insights into the fundamental laws of nature. Find out more on http://home.cern.
Introduction
We seek a talented and experienced ASIC Digital Designer with expertise in digital-on-top (DoT) implementation and System-on-Chip (SoC) design techniques. The candidate will contribute to ASIC development for particle physics experiments, working with advanced CMOS technologies (e.g., 65nm, 28nm) in collaboration with system architects, analogue and mixed-signal designers, and verification engineers.
You will join the Electronic Systems for Experiments Group (ESE) within the Experimental Physics Department (EP), which designs electronic systems, including ASICs, for CERN's experiments and provides related services. The Microelectronics section (ME) develops analogue and digital ASICs for CERN's particle detectors.
Functions
As an ASIC Digital Designer, you will:
* Perform full-chip digital integration and verification, including:
o incorporating custom logic, third-party IP blocks, and standard interfaces
o managing clock/reset domains
o applying low-power design techniques
* Develop RTL code ensuring synthesizable and reusable designs.
* Create high-level architectures for ASICs, including SoC partitioning, data paths, control logic, and interfaces.
* Write testbenches and run simulations to verify design functionality.
Applicants should have a Master's degree, PhD, or equivalent experience in Electronics Engineering or a related field.
Experience
The required experience includes:
* Hierarchical DoT ASIC integration and implementation from RTL to GDS, including verification.
* Proficiency with advanced EDA tools and deep submicron CMOS technologies, such as Cadence tools and process nodes like 65nm, 28nm, or smaller.
* RTL design (Verilog/SystemVerilog) and scripting (Python, TCL, Shell).
* Logic synthesis, timing closure, STA, and power integrity analysis.
* Physical design, floorplanning, placement, routing, and sign-off checks.
* Developing test benches for behavioral and functional simulations.
* Integrating analog and digital IPs, managing interconnects, clock/reset domains, and timing constraints.
* Design-for-testability (DFT) structures and manufacturing methodologies.
Additional valued experience includes:
* SoC design techniques, bus protocols (AXI, AHB, APB).
* RISC-V ISA and core integration.
* Microarchitecture design, debugging tools, FPGA prototyping, radiation effects mitigation, high-level description languages, signal integrity, and testing.
Key competencies include teamwork, result orientation, flexibility, effective communication, and knowledge sharing. Proficiency in English (spoken and written) is required, with a commitment to learn French.
Eligibility and closing date:
CERN values diversity and welcomes applications from all Member and Associate Member States. Applications should be submitted by 25.05.2025, 23:59 CEST.
Employment Conditions
* Limited duration contract (5 years), with potential for indefinite employment.
* 40 hours/week.
* Work in radiation areas, including nights, Sundays, and holidays if required.
Job grade: 6-7
Job reference: EP-ESE-ME-2025-85-LD
Benchmark Job Title: Electronics Engineer
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